1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices and manufacturing methods thereof.
2. Description of the Background Art
A nonvolatile semiconductor memory device according to a conventional art and a method of manufacturing the nonvolatile semiconductor memory device are described below in conjunction with FIGS. 9A-9D to FIGS. 21A-21D and FIGS. 22-24. The nonvolatile semiconductor memory device includes two regions, i.e., a memory cell region and a peripheral circuitry region. In FIGS. 9A-9D to FIGS. 21A-21D, xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d (e.g. FIGS. 9A and 9B, 10A and 10B . . . ) represent the peripheral circuitry region and xe2x80x9cCxe2x80x9d and xe2x80x9cDxe2x80x9d (e.g. FIGS. 9C and 9D, 10C and 10D . . . ) represent the memory cell region. Further, xe2x80x9cAxe2x80x9d (e.g. FIGS. 9A, 10A . . . ) represents an NMOS transistor region 200 and xe2x80x9cBxe2x80x9d (e.g. FIGS. 9B, 10B . . . ) represents a PMOS transistor region 100 that are included in the peripheral circuitry region. A cross section in parallel with word lines of the memory cell region is represented by xe2x80x9cCxe2x80x9d (shown in FIGS. 9C, 10C . . . ) and a cross section in parallel with bit lines thereof is represented by xe2x80x9cDxe2x80x9d (shown in FIGS. 9D, 10D . . . ).
Referring to FIGS. 9A-9D, an isolation oxide film 2 is formed at a main surface of a silicon substrate 1. A resist (not shown) is formed on the entire main surface of silicon substrate 1. Apart of the resist that is formed on PMOS transistor region 100 is removed. The remaining resist is used as a mask to carry out ion implantation under the conditions of 1.2 MeV and 1.0xc3x971013 cmxe2x88x922, for example, for implanting phosphorus as impurities and thus form an N well 3. Further, phosphorus ions are implanted for channel cutting of isolation oxide film 2 under the conditions of 700 keV and 3.0xc3x971012 cmxe2x88x922 for example, and boron ions are implanted for channel doping of the surface layer under the conditions of 20 keV and 1.5xc3x971012 cmxe2x88x922 for example. The resist is then removed to obtain N well 3 in PMOS transistor region 100 as shown in FIGS. 10A-10D.
A resist (not shown) is formed on the entire main surface of silicon substrate 1. A part of the resist that is formed on NMOS transistor region 200 and the memory cell region is removed. The remaining resist is used as a mask to carry out ion implantation under the conditions of 700 keV and 1.0xc3x971013 cmxe2x88x922, for example, for implanting boron as impurities and thus form a P well 4. Further, boron ions are implanted for channel cutting of isolation oxide film 2 under the conditions of 270 keV and 3.5xc3x971012 cmxe2x88x922 for example, and boron ions are also implanted for channel doping of the surface layer under the conditions of 50 keV and 1.2xc3x971012 cmxe2x88x922 for example. The resist is thereafter removed to obtain P well 4 in NMOS transistor region 200 and the memory cell region as shown in FIGS. 11A-11D.
On the entire exposed part of the main surface of silicon substrate 1, a silicon oxide film 5 is formed to a thickness of 100 xc3x85 by thermal oxidation. Silicon oxide film 5 is to be used as a tunnel oxide film. A phosphorus-doped polycrystalline silicon layer 6 is further formed to cover the upper side of silicon oxide film 5 to a thickness of 1000 xc3x85 by low-pressure CVD (Chemical Vapor Deposition) for the polycrystalline silicon film. By means of photolithography, a predetermined patterning process is conducted to etch phosphorus-doped polycrystalline silicon layer 6 of the memory cell region. After this etching, silicon oxide film 5 and phosphorus-doped polycrystalline silicon layer 6 of the peripheral circuitry region are left as they are. Then, by means of ion implantation, arsenic ions are implanted under the conditions of 40 keV and 2xc3x971015 cmxe2x88x922 for example to form n-type diffusion layers 7a and 7b in the memory cell region. In this way, the structure as shown in FIGS. 12A-12D is completed.
A silicon oxide film of 50 xc3x85 in thickness by thermal oxidation, a silicon nitride film of 100 xc3x85 in thickness by low-pressure CVD and a silicon oxide film of 50 xc3x85 in thickness by low-pressure CVD are formed in this order and accordingly, a three-layer insulating film 8 (also referred to as xe2x80x9cONO filmxe2x80x9d) is produced. The structure as shown in FIGS. 13A-13D is thus completed.
By means of photolithography, a resist is formed to partially cover the memory cell region, and three-layer insulating film 8, phosphorus-doped polycrystalline silicon layer 6 and silicon oxide film 5 in the peripheral circuitry region are removed. Then, the structure as shown in FIGS. 14A-14D is completed.
Thermal oxidation is used to grow a silicon oxide film 9 to a thickness of 150 xc3x85, that is to be used as a gate electrode of a transistor of the peripheral circuitry region. In the memory cell region at this stage, the silicon nitride film of three-layer insulating film 8 prevents underlying phosphorus-doped polycrystalline silicon layer 6 from being thermally oxidized. Then, by means of low-pressure CVD, a phosphorus-doped polycrystalline silicon layer 10 of 2000 xc3x85 in thickness and a silicon oxide film 11 of 2000 xc3x85 in thickness are deposited. A resist with a desired pattern is formed by photolithography, and this resist is used as a mask to pattern silicon oxide film 11. After removal of this resist, silicon oxide film 11 is used as a mask to pattern phosphorus-doped polycrystalline silicon layer 10 that is to be used as a gate electrode of a transistor of the peripheral circuitry region. Simultaneously, phosphorous-doped polycrystalline silicon layer 10 is also patterned that is to be used as a control electrode of a transistor of the memory cell region. In this way, the structure as shown in FIGS. 15A-15D is completed.
A resist is formed to cover the peripheral circuitry region, and silicon oxide film 11 of the memory cell region is used as a mask to etch three-layer insulating film 8 and phosphorus-doped polycrystalline silicon layer 6 and accordingly form a floating gate electrode of a transistor of the memory cell region. The structure as shown in FIGS. 16A-16D is accordingly completed.
A resist is further formed by photolithography to cover PMOS transistor region 100 and the memory cell region. The resist is used as a mask to implant phosphorus ions of 2xc3x971013 cmxe2x88x922 with 70 keV energy. Consequently, a low-concentration n-type diffusion layer 12 of an N channel transistor is formed in NMOS transistor region 200. The resist is thereafter removed and the structure as shown in FIGS. 17A-17D is completed.
By photolithography, a resist is formed to cover NMOS transistor region 200 and the memory cell region. The resist is used as a mask to implant BF2 ions of 7xc3x971012 cmxe2x88x922 with 70 keV energy. As a result, a low-concentration p-type diffusion layer 13 of a P channel transistor is formed in PMOS transistor region 100. The resist is then removed and the structure as shown in FIGS. 18A-18D is completed.
By CVD, a silicon oxide film is deposited to a thickness of 2000 xc3x85. Anisotropic etching of this silicon oxide film produces a sidewall spacer 14. By photolithography, a resist is formed to cover PMOS transistor region 100 and the memory cell region. This resist is used as a mask to implant arsenic ions of 3xc3x971015 cmxe2x88x922 with 50 keV energy. The resist is then removed. By photolithography again, a resist is formed to cover NMOS transistor region 200 and the memory cell region. The resist is used as a mask to implant BF2 ions of 3xc3x971015 cmxe2x88x922 with 30 keV energy. The resist is removed and thus the structure shown in FIGS. 19A-19D is completed. In this structure, a high-concentration n-type diffusion layer 15 of the N channel transistor and a high-concentration p-type diffusion layer 16 of the P channel transistor are formed.
By CVD, a boron-phosphorus glass 17 is deposited to a thickness of 10000 xc3x85. By annealing in a nitrogen atmosphere at 850xc2x0 C. for 30 minutes, the boron-phosphorus glass is hardened or annealed and thereafter a resist with a desired pattern is formed by photolithography. This resist is used as a mask to etch the boron-phosphorus glass and accordingly make a contact hole 20.
By photolithography, a resist is formed to cover NMOS transistor region 200 and the memory cell region. Then, boron of 1xc3x971015 cmxe2x88x922 is implanted with 50 keV energy for generating an ohmic contact. The resist is then removed. By photolithography again, a resist is formed to cover PMOS transistor region 100, phosphorus of 1xc3x971015 cmxe2x88x922 is implanted with 70 keV energy for generating an ohmic contact and then the resist is removed. In this way, the structure shown in FIGS. 20A-20D is completed.
By sputtering, an aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) alloy film is deposited. By photolithography, a resist with a desired pattern is formed, and this resist is used as a mask to etch the Alxe2x80x94Sixe2x80x94Cu alloy film. An Alxe2x80x94Sixe2x80x94Cu interconnect 21 is accordingly formed as shown in FIGS. 21A-21D.
The nonvolatile semiconductor memory device is thus produced.
A memory transistor of the nonvolatile semiconductor memory device is usually operated as described below. For programming (writing) of the memory transistor, a high voltage of approximately 20 V is usually applied to control gate electrode 10 to ground n-type diffusion layers 7a and 7b and silicon substrate 1. Accordingly, electrons are generated in a channel formed in the region between n-type diffusion layers 7a and 7b. The electrons tunnel through an energy barrier formed by tunnel oxide film 5 to enter floating gate electrode 6. As a result, the threshold voltage of a memory cell increases to Vthp.
On the contrary, for erasing, a high voltage (usually about xe2x88x9220V) is applied to control gate electrode 10 to ground n-type diffusion layers 7a and 7b and silicon substrate 1, and a resultant tunnel phenomenon causes electrons to be discharged from floating gate electrode 6 into silicon substrate 1. Consequently, the threshold voltage of the memory cell decreases to Vthe.
For reading of a selected memory transistor, 3.3 V is applied to control gate electrode 10 and 3.3 V is also applied to n-type diffusion layer 7a which is drain, for example, so as to ground n-type diffusion layer 7b which is source and silicon substrate 1. Here, it is supposed that there exists a relation Vthp greater than 3.3 V greater than Vthe. Then, no current flows between the source and drain of the memory transistor in a programmed state and current flows therebetween of the memory transistor in an erased state.
For a memory transistor which is not selected for reading, control gate electrode 10 is grounded, and 3.3 V is applied to n-type diffusion layer 7a which is the drain to ground n-type diffusion layer 7b which is the source and silicon substrate 1. As a relation Vthp greater than Vthe greater than 0 is established, no current flows between the source and drain of the memory transistor when zero voltage is applied to control gate electrode 10.
Accordingly, only a selected memory transistor in a programmed state among memory transistors, current flows between the source and drain and thus information of each memory cell is defected.
For the nonvolatile semiconductor memory device, high voltage is used for writing and erasing as described above. Then, a transistor of the peripheral circuitry region must have a structure resistant to such high voltage. According to the conventional art, an LDD (Lightly Doped Drain) structure as shown in FIGS. 21A and 21B is employed so as to constitute a high breakdown-voltage transistor.
Here, the high breakdown-voltage transistor is described. The breakdown voltage of transistors is generally classified into the one called xe2x80x9cOFF breakdown voltagexe2x80x9d and the one called xe2x80x9cON breakdown voltage.xe2x80x9d OFF breakdown voltage refers to a breakdown voltage between the source and drain when voltage of 0 V is applied to the gate electrode. ON breakdown voltage refers to the minimum breakdown voltage between the source and drain when the voltage applied to the gate electrode is varied.
When a transistor is operating, the breakdown voltage between the source and drain has a mechanism which is one type of parasitic bipolar effects as analyzed by E. Sun, J. Moll, J. Berger and B. Alders in xe2x80x9cBreakdown Mechanism in Short-Channel MOS Transistorsxe2x80x9d (IEEE Tech. Dig., International Electron Device Meeting, Washington D.C., 1978, p.478). For a short-channel MOSFET, when a drain voltage is increased, an electric field in the channel direction remarkably increases in the vicinity of the drain so that an avalanche breakdown phenomenon arises. Accordingly, a great number of carriers, namely electron-hole pairs are generated. Holes of the generated electron-hole pairs flow to a p-type silicon substrate to constitute substrate current Isub and a part of the holes flows into an n-type source region. The hole current flowing into the n-type source region causes the voltage in the vicinity of the n-type source region to decrease so that the potential difference between the n-type source region and the p-type silicon substrate exceeds the built-in potential (potential barrier) of the pn junction between the source region and the substrate. Then, forward current begins to flow through the pn junction between the source and substrate. In other words, electrons flow from the n-type source region into the p-type silicon substrate so that a parasitic bipolar transistor operation formed of the source-substrate-drain occurs. Consequently, a breakdown phenomenon of the MOS transistor occurs. The breakdown phenomenon occurs under a condition as represented by the following formula for example:
IHxc2x7Rsub greater than Vbuilt-in 
where IH denotes current flowing into the source, Rsub denotes resistance along a path through which holes flow between the substrate and source, and Vbuilt-in denotes built-in potential of the pn junction between the substrate and source.
It is accordingly found that, in order to improve the breakdown voltage of a transistor, i.e., in order to make the breakdown phenomenon less likely to occur, decrease of hole current IH generated due to the avalanche breakdown phenomenon is critical. Substrate current Isub consisting of the great majority of the generated hole current serves directly as a barometer of the avalanche breakdown phenomenon and also serves as an important parameter used for predicting hot carrier deterioration. The substrate current greatly depends on the maximum field intensity in the source-drain direction (hereinafter xe2x80x9cchannel directionxe2x80x9d) in the vicinity of the drain and generally represented by the following formula:
Isubxe2x88x9dIdxc2x7Em 
where Id denotes drain current and Em denotes the maximum field intensity in the channel direction. It is accordingly found that the maximum field intensity Em may be reduced for decreasing the substrate current (hole current).
Then, for a transistor having the LDD structure explained above, the maximum field intensity Em can be reduced by increasing the width of the low-concentration diffusion layer. Here, xe2x80x9cwidth of low-concentration diffusion layerxe2x80x9d refers to the width of the portion where the low-concentration diffusion layer is present along a current path in the source-drain direction. In this way, a depletion layer can be extended sufficiently into the low-concentration diffusion layer and thus the field intensity in the corresponding portion can be decreased. FIG. 22 shows a graph disclosed by Koyanagi, Kaneko and Shimizu in xe2x80x9cDigest of 1983 Autumn Annual Meeting of the Japan Society of Applied Physicsxe2x80x9d indicating the field intensity at each position for several widths of the low-concentration diffusion layer. In this graph, Lsw denotes the length of one side, in the channel direction, of the low-concentration diffusion layer. As seen from this graph, increase of the width of low-concentration diffusion layer in the channel direction provides enhancement of the breakdown-voltage property of a transistor.
The low-concentration diffusion layer has a relatively high resistance. Then, increase of the width of this region causes the drain current to decrease as shown in FIG. 23. This means that the transistor has a deteriorated current drivability which results in a lower reading speed for example. However, the deteriorated current drivability presents no problem since it takes a long time, in writing and erasing operations essentially requiring a high breakdown-voltage, to implant electrons into the floating gate and draw electrons from the floating gate.
One object of the present invention is accordingly to provide a nonvolatile semiconductor memory device satisfying requirements of both of a high breakdown-voltage transistor which needs no current-drive power and a transistor which needs no high-breakdown voltage while it requires the current-drive power. Another object of the present invention is to provide a method of manufacturing the nonvolatile semiconductor memory device which can form both of such transistors without addition of any extra process step to the conventional manufacturing method.
According to one aspect of the present invention, in order to achieve the objects above, a nonvolatile semiconductor memory device includes a semiconductor substrate having a main surface and a plurality of transistors formed on the main surface. The transistors each include a gate electrode, a diffusion layer formed adjacent to the gate electrode, and contacts communicating with the diffusion layer. The contacts corresponding to the transistors include contacts at a first distance from the gate electrode and contacts at a second distance, longer than the first distance, from the gate electrode. This structure can be used to implement transistors in which the distance between a contact and a gate electrode can be determined according to characteristics required of the transistors respectively and thus the transistors can meet various needs.
Preferably, according to the present invention, the transistors include a normal transistor having its interconnection for applying the normal transistor with only a voltage of at most a predetermined first level so as to operate the normal transistor, and a high breakdown-voltage transistor having its interconnection for applying the high breakdown-voltage transistor with a voltage of a second level higher than the first level. The contacts of the normal transistor are each at the first distance from the gate electrode, and the contacts of the high breakdown-voltage transistor include a contact at the second distance from the gate electrode. This structure can be used to make longer the gate-contact distance of the high breakdown-voltage transistor than that of the normal transistor. Then, the width of diffusion layer of the high breakdown-voltage transistor can be kept large in order to enhance the breakdown-voltage property of the high breakdown-voltage transistor.
Preferably, according to the present invention, the high breakdown-voltage transistor includes a transistor having the contacts located on two lateral sides of the transistor, and one of the contacts is at the first distance from the gate electrode and the other contact is at the second distance from the gate electrode. This structure can be used to allow a high breakdown-voltage transistor, which has source and drain never replaced with each other, to have a longer distance between the gate electrode and contact where the high breakdown-voltage is necessary. Then, the high breakdown-voltage can be achieved in only a portion requiring it.
According to another aspect of the present invention, in order to achieve the objects above, a nonvolatile semiconductor memory device includes a semiconductor substrate having a memory cell region and a peripheral circuitry region, a first transistor placed at the memory cell region and on the semiconductor substrate, and second and third transistors placed at the peripheral circuitry region and on the semiconductor substrate. The first transistor serves as a nonvolatile memory device capable of writing, erasing and reading information by being applied with a predetermined voltage. The second and third transistors each include a gate electrode formed on a main surface of the semiconductor substrate, a first pair of diffusion layers formed by implanting impurities with a first concentration into respective active regions adjacent to two lateral sides respectively of the gate electrode, an interlayer insulating film formed to cover the gate electrode and the first pair of diffusion layers, and paired contacts electrically connected respectively to the diffusion layers of the first pair of diffusion layers through the interlayer insulating film. The paired contacts include respective contact bodies extending upward from the main surface and respective contact-connected diffusion layers formed by implanting impurities with a second concentration higher than the first concentration locally into respective regions in the vicinity of respective contact regions between the contact bodies and the semiconductor substrate. The second transistor has its interconnection for applying the second transistor with only a voltage of at most a predetermined first level so as to operate the second transistor. The third transistor has its interconnection for applying the third transistor with a voltage of a second level higher than the first level when at least one of writing and reading of the first transistor is performed. A contact of the paired contacts of the third transistor that is applied with the voltage of the second level serves as a high breakdown-voltage contact, a contact except for the high breakdown-voltage contact of the second and third transistors serves as a normal contact, and the distance between the gate electrode and a corresponding contact-connected diffusion layer of the high breakdown-voltage contact is longer than the distance between the gate electrode and a corresponding contact-connected diffusion layer of the normal contact. This structure can be used to make longer the width of low-concentration diffusion layer corresponding to the first pair of diffusion layers in a high breakdown-voltage transistor region so that the maximum field intensity Em can be decreased in this region. Accordingly, the breakdown-voltage property can be improved. In a high drive-power transistor region, the width of low-concentration diffusion layer is smaller so that the drain current does not decrease and the operating speed can be kept high.
Preferably, according to the present invention, the contact-connected diffusion layers of the second and third transistors are each an impurity layer formed by implanting impurities through each contact hole for the paired contacts. The distance between the gate electrode and the high breakdown-voltage contact of the third transistor is longer than the distance between the gate electrode and the normal contact of the second and third transistors. This structure can be used to implant impurities through a contact hole to generate the contact-connected diffusion layer serving as a high-concentration diffusion layer of the conventional LDD structure. Then, no sidewall is necessary that is required for producing the conventional LDD structure. The manufacture is thus facilitated since just a change is necessary to the positions of contact holes in order to implement a high breakdown-voltage transistor.
Preferably, according to the present invention, the second transistor includes a sidewall spacer covering a sidewall of the gate electrode. The contact-connected diffusion layers of the second transistor are included in the first pair of diffusion layers, the contact-connected diffusion layers constituting a second pair of diffusion layers formed by implanting impurities into respective regions exposed on the main surface and located adjacent to the outside of the sidewall spacer. This structure can be used to produce the second pair of diffusion layers by implanting impurities with the sidewall as a mask, for the second transistor, namely the normal transistor, and thus produce the LDD structure. It is unnecessary to make a contact hole close to the gate electrode for preventing the drive current from decreasing. The thickness of the sidewall determines the width of low-concentration diffusion layer so that the drive current can be kept constant.
Preferably, according to the present invention, the contact-connected diffusion layers of the third transistor are each an impurity layer formed by implanting impurities through each contact hole for the paired contacts. The distance between the gate electrode and the high breakdown-voltage contact of the third transistor is longer than the distance between the gate electrode and the normal contact of the third transistor. This structure can be used to produce the second transistor with the LDD structure so as to allow the second transistor to have a constant drive current. The third transistor has the contact produced distantly from the gate electrode so that the width of low-concentration diffusion layer can be kept long and thus the breakdown-voltage property can be improved.
According to the present invention, in order to achieve the objects above, a method of manufacturing a nonvolatile semiconductor memory device including a plurality of transistors formed on a main surface of a semiconductor substrate, the plurality of transistors including a gate electrode and a diffusion layer formed adjacent to the gate electrode, and the transistors including a first group of transistors and a second group of transistors, the method including the step of forming contact holes of the first group of transistors at a first distance from the gate electrode and forming contact holes of the second group of transistors at a second distance, longer than the first distance, from the gate electrode. This method can be used to allow the first group of transistors to serve as normal transistors and allow the second group of transistors having a longer gate-contact distance to serve as high breakdown-voltage transistors. These normal and high breakdown-voltage transistors can accordingly be produced simultaneously through the same process steps.
Preferably, according to the present invention, the transistors of the first group are each serve as a normal transistor having its interconnection for applying the normal transistor with only a voltage of at most a predetermined first level so as to operate the normal transistor, and the transistors of the second group are each serve as a high breakdown-voltage transistor having its interconnection for applying the high breakdown-voltage transistor with a voltage of a second level higher than the first level. This method can be used to make longer the gate-contact distance and thus achieve a high breakdown-voltage in a transistor applied with a high voltage, since whether a transistor is a high breakdown-voltage transistor or not is determined depending on whether the transistor is applied with a high voltage of the second level.
Preferably, according to the present invention, at least a part of the transistors of the second group each includes the contact holes formed on two lateral sides of the transistor, one of the contact holes is formed at the first distance from the gate electrode and the other contact hole is formed at the second distance from the gate electrode. This method can be used to allow a transistor with only one side applied with a high-voltage to have a longer gate-contact distance where a high breakdown-voltage is required. Then, the high breakdown-voltage can be achieved for only a portion requiring it.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.